The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a vertical transistor containing a strained semiconductor material channel pillar flanked on either side by a functional gate structure. The present application also relates to a method of forming such a vertical transistor.
Conventional vertical transistors are devices where the source-drain current flows in a direction normal to the substrate surface. In such devices, a vertical semiconductor pillar defines the channel with the source region and the drain region located at opposing ends of the semiconductor pillar. One advantage of vertical transistors is the decoupling of the gate length from the contact gate pitch. Therefore, vertical transistors have been explored as a viable device option for continued complementary metal oxide semiconductor (CMOS) scaling beyond the 7 nm technology node.
Strain engineering is highly desired for enhancing carrier mobility and thus the drive current of vertical transistors. Unlike conventional horizontal transistors, it is very difficult to maintain the strain in a vertical semiconductor pillar that defines the channel of the vertical transistor because vertically standing semiconductor pillars will become relaxed regardless of their initial strain status. There is thus a need for forming a vertical transistor while preserving the strain of the vertical semiconductor pillar that defines the channel of the vertical transistor throughout the entire fabrication process.